Episode 874 transcript

FLOSS-874

Jonathan: Hey folks. This week I'm talking with Andrea Gallo of RISC-V International. We talk all about everyone's favorite open ISA, the fact that there might be more RISC-V cores in the world than there are people, and lots more. You don't wanna miss it, so stay tuned. This is Floss Weekly, episode 874, recorded Tuesday, July the 7th.

Really, we do PDFs It's time for Floss Weekly. That's the show about free, libre, and open source software. I'm your host, Jonathan Bennett, and today we're gonna be a little risky today. We're talking about RISC-V. I, I had to make the pun. I know. I'm sorry. I'm a dad. I make dad jokes. Anyway, we're talking about RISC-V, the open ISA, the open ecosystem.

And we've got somebody, we have somebody very special from RISC-V International and from various places. He does a lot of things. It's it's the man when you talk about RISC-V. We have we have Andrea Gallo. I think I got that did I pronounce that right, sir?

Andrea: Perfect.

Yeah, perfect.

Jonathan: Okay. Excellent. Perfect. Excellent. And where I forget to ask this sometimes, but where are you speaking to us from? Where are you at in the world?

Andrea: I'm just close to Milan, Italy.

Jonathan: Oh. Oh, my goodness. You lucky dog. That's awesome. I'm in Southwest Oklahoma, which has its own charms.

A business colleague of mine- Of course ... just the other day was driving through Oklahoma, and they stayed at a, he stayed at a little tiny town with his family in Oklahoma. And he's "Oklahoma's really nice." I tried to tell you it's really nice here. So Andrea, y- you are you're now the, let's see, the CEO at RISC-V International, and I have about three different questions that go along with that.

And I think the first one is what's your background? Y- if I remember correctly, you're you've come from the technical side of things, not the- ... i, I don't mean to be derogatory here, but not the bean counter side of the house. What i- what has that been like to go from the very technical side of things to you're now CEO of this huge organization?

Andrea: Oh it's a big honor and quite a challenge, of course. Yeah, I have a mixed background of hardware and software for- ... for, since the beginning I've always messed up because I always enjoyed mixing the hardware side and the software side- ... in many different roles. And I've al- always enjoyed facing customers as well.

So I started as application engineer in my early professional days. But even before that I was writing little games that were published by one of those old style magazines where you had all the listings, and so I always enjoyed the public facing side as well. And I was also responsible for business development in a previous professional role.

So I always enjoys the mix of both technical and customer facing.

And,

Jonathan: I was thinking as you were saying that, th- there, there's some combinations that c- give you superpowers. For example I've, one of the lawyers that I work with, she's also studying to be a CPA, and o- once you have both passed the bar and passed the CPA exam in the US you're a superhero in the legal world.

And I think in the software hardware world, someone that has written firmware and dabbled with software, has done hardware designs being able to do both of those sort of gives you a superpower. And then on top of that, you also do the business side of things. No wonder they made you the CEO.

Andrea: No, the real guys are the founders of RISC-V, and all the great minds on the technical steering committee that drive the work on RISC-V. Those are the real brains. I think at RISC-V International, we're just serving these big brains. That's our role, help them achieve what they are, they're really doing.

Jonathan: So that's a, that's actually a really good segue. What is RISC-V International? How does it fit into the puzzle of what RISC-V is?

Andrea: RISC-V International is the nonprofit association is the organization that hosts and coordinates the evolution of the RISC-V ISA. So we ensure that the evolution of the specifications is done in full coherence with the missions and standards set by the original founders of RISC-V and we ensure that there are no deviations along the path and that we ensure that the process follows the right policies and procedures, and it's transparent and collaborative.

I think our role is to ensure that all the members that found the work at RISC-V, they collaborate in a constructive and positive environment. So we have RISC-V International to thank for things like RVA23? For example so we as a nonprofit organization, we are funded by all the commercial companies that design products based on RISC-V or IPs based on RISC-V.

But we also benefit from the collaboration of nonprofit and academia institutions and some very skilled individuals. And we are uniformly distributed worldwide. I've been traveling a lot for the very r- RISC-V summits and for other industry events, and also visiting multiple academia.

And I can tell you that it's it's so rewarding. It's such a pleasure to see that you can face the same level of technical competence and maturity in understanding and adopting RISC-V, the same level worldwide. From the US to Europe to Asia to Brazil all these students studying RISC-V at classes, at courses using RISC-V for their projects, for their master thesis.

It's unbelievable. And even on the daily work at RISC-V in the technical working groups, when we... in the end we do PDF. If I oversimplify, what we do is that we deliver PDF. That's all we do. That's fair. That's what we do. PD- PDF. That's fair. So when we, on a daily basis on the technical working groups I see the conversations from all these great minds and I don't see one geography producing more or contributing more to the specifications and one geography consuming more.

Not at all. I see the same level of interaction and collaboration across all. Do,

Jonathan: do you think the open s- the open nature of the ISA is to to, to blame i- is what causes that? So many people know about it because it's open and it's taught in academia and it gets used everywhere.

Andrea: First of all, just along the lines of I was saying we, we do PDF I would like to add that we focus on the standards. We like to make the reference to the USB or the Wi-Fi standards. Behind me I have some products that I designed many years ago that were, they were based on the USB specifications.

And you can download the USB specifications from the website wherever you are, and the same is true for RISC-V. You can freely download the RISC-V ISA specifications wherever you are in the world, and then locally you would invest in designing your IPs or products locally where you are. So it's important because these, Reinforces the message that RISC-V is an industry standard.

And this was also recognized by ISO last year. 2020- September 2025, the ISO/IEC, the joint technical committee recognized RISC-V International as a PAS submitter. PAS stands for publicly available specification. It was quite a long effort and helped us improve as well the way we work in tracking participation from all the members, in logging consensus from the members, in ratifying the specifications.

And all this has been recognized as a transparent and and fully correct way of working, aligned to the ISO/IEC guidelines. So we got recognized as a, as somewhat as a standardization body.

And the next step for us is to submit the RISC-V specification, the ISA manuals, to be evaluated and hopefully ratified as an ISO standard in the future.

So I, I was just adding this as an important point for us that RISC-V is a standard. It is not an implementation. There are many implementations done by the members.

Jonathan: I think that's a, I think that's an im- important point to make and to step into, and I was thinking about asking you the question, the leading question because the ISA is open, that means that all of the RISC-V hardware out there is open source hardware, right?

Not quite.

Andrea: I ... No, not quite, and I really like the question. Not quite. From the standard Then you can have all of business models. You can have a pure open source implementation done by academia or by companies that offer an open source implementation, and then offer commercial services to customize or productize it.

Or you can have a fully closed commercial IP designs for licensing. All options are possible, from a pure open source academia to a fully closed commercial. But I also like the hybrid model. If you think about it companies in the open source space companies like Red Hat or Canonical or others, in a way they all invest in open source software.

They sell you a subscription to their operating system distributions, and then they also offer you commercial services to integrate that into your s- software products. And this is this is an option for some of the RISC-V members, have an open source RISC-V implementation and commercial support services.

Or fully commercial. So all the shades of colors are possible.

Jonathan: And so when we talk about the RISC-V ISA that, that's essentially like the definition of the instruction set and like the definition of what each of those instructions are supposed to do, right?

Andrea: Yes.

Exactly. Okay. Exactly.

Jonathan: Exactly. And so you can implement that. Someone can implement a f- fully to spec RISC-V implementation in an FPGA, in silicon. I'm sure- Yes ... someone has tried to do a minimum version of it in vacuum tubes or, people do crazy stuff just because they can. So there's a bunch of RISC-V all around us.

Andrea: Yes. And even more on our website. We offer free training courses. One of them is one of my favorites. I took it during my interview process actually to get the job. And the train ... the course was Design your RISC-V CPU core, and it guides you from reading the ISA specifications- understanding them, designing the instruction decoder, designing the register file, and an example of a very simple single stage, single clock cycle e- execution unit. And you do everything in a browser. You get all the environment the system Verilog, the compiler, the emulators, and you can even run some simple assembly software to try it out.

A- and this is a course that I recommend to all the hardware and software engineers, both.

Jonathan: Yeah, that's very cool. I went through... In fact, we've interviewed him on the show. There's a similar idea called NAND to Tetris, and they start with the NAND gate, and it's "Okay, here's how you put two NAND gates together to get a NOT gate," and, all of those different things.

Yes. And it gets all the way up to now program your Tetris game on your operating system that runs on the CPU that you built. Excellent. I don't remember if that uses the RISC-V ISA or not, it, but it's gonna be similar. I love those sorts of things, though, because you s- you start with the very basics and you build each layer up- Yes

and so you get to the point to where you understand the whole stack.

Andrea: Yes. W- And you appreciate the simplicity. I've, I worked on many different ISAs over, over the years, from CISC to RISC many different ones, and I really enjoyed looking at the hardware side of RISC-V, how simple it is from the op codes, the instructions, the bit fields, to write the instruction decoder.

It's class. It's really classy. I think Krste Zaninović, Andrew Waterman, Yoon Soplee, Dave Patterson, they did something amazing with this RISC-V ISA.

Jonathan: So it's RISC-V, which brings the question to mind, was there a RISC-IV?

Andrea: Yes. Yes. Actually it all started with a RISC-I in the early '80s.

Actually in the early '80s Dave Patterson wrote a paper making the case for RISC, reduced instruction set computing, and then the RISC-I was the very first chip as the very first proof of concept. And then there were a few other iterations done at UC Berkeley under the direction of Dave Patterson.

And in 2010 the work started on the fifth generation, so the V in RISC-V, the V sta- is the Roman number for fifth generation. But we also joke that is also reminds V for vectors, because RISC-V has been designed since the beginning to have the most flexible vector extension design.

Jonathan: Interesting.

That and that's part of what RVA23 is about, isn't it? Is additional support for doing vector instructions?

Andrea: RVA23 is a profile specification. Let's see. RISC-V is very modular. You have many extensions that add small features or security or performance, and they're all modular, and you can

It's like ingredients in a recipe. And you can build your RISC-V microcontroller that is perfectly handcrafted for your specific workload or application or specific function. But then, yes, everyone may have a different recipe. RVA23 standardizes the non-differentiating bits- ... and sets the bar high for a high-performing application processor.

So when you are when you own your design, you want to optimize it at best for your specific application that you fully own, hardware and software. Then RISC-V gives you this flexibility, and you can add your specific custom instructions for that specific function, the, and you will get the most optimized design.

But if you want to run a standard operating system, like Linux or an RTOS, you are not going to port it Once for every single vendor. That would not be sustainable. That would lead to unnecessary fragmentation. And this is what RVA23 solves. RVA23 defines the minimum set of extensions that shall all be present as mandatory, as regional options, as growth options- that shall all be present in a design, in an RVA23 application processor. And this means that the operating system vendors can target RVA23 at the single build target, and you will get binary application compatibility. A- and this has been ... This has worked really well because Canonical immediately endorsed it.

And Ubuntu- I was

Jonathan: at, I was at the Ubuntu Summit at, the ... Where they, where they d- released that. They made that announcement, and then they- Yeah ... they had a f- ... Was it Space MIT? One of the, one of the companies had- Yes ... some hardware there. Yes. And I was like, "Ooh- Yes ... I can take this home with me, right?"

And they're like, "No, you don't get to take that home."

Andrea: No, but you will get access very soon-

Jonathan: Yes ... to that one. Yes. Yes. I immediately sent- So it- I immediately sent a message to one of my developers. I'm like, "Hey, send an email to these guys and ask them for hardware." Yes.

Andrea: No, th- that's exactly the point, and Ubuntu now runs on every RVA23 compliant design.

And similarly, Nvidia disclosed ... Last year, they disclosed plans to port CUDA to RVA23. So you do the port once, you do the work once- ... and it works on all the RVA23 compliant application processors.

Jonathan: Yeah, absolutely. What what are some of the challenges? You mentioned fragmentation, and that was something I was going to ask about.

But i- and we can d- dive a little bit more into that if you want to, but I'm curious if there are some other challenges right now in the RISC-V ecosystem doing d- doing this development or even trying to work with the other companies out there.

Andrea: I would say that we are working in expanding RISC-V from a horizontal technology.

In deeply embedded microcontroller or security processors or AI specific schedulers, for example. We are expanding RISC-V into multiple different vertical industry verticals and so we, we introduced the concept of the special interest groups at RISC-V. So we started with the data center, with the automotive special interest group.

End of 2025, we s- we launched a space interest group. The concept is that you invite the domain specific experts who come in with the domain specific requirements, and maybe they are new to RISC-V, so they need help. I remember in the early days two years ago, the questions was, for example if we want to design an ECU based on RISC-V, how do we run AUTOSAR on RISC-V?

How do we achieve the right physical memory partitioning or protection? How do we run a trusted execution environment on RISC-V? And then we bring in the technical experts, and it's like matchmaking. And by mapping the requirements to the RISC-V technologies, then we come up with a gap analysis.

We may identify low-hanging fruits for innovation. And we also write application notes that they explain how to configure RISC-V at best for each each vertical. So in the automotive space we're working on, first of all, functional safety. We have a white paper with a functional safety special interest group and experts in functional safety.

Where we find that there are no gaps. And then in automotive in addition, how to configure RISC-V for an ECU microcontroller, or for a zonal controller, or for the central compute in automotive. Similarly in space I find it quite interesting and amusing. For me, SaaS means Software as a Service.

But in the space world, for for our friends and colleagues and members i- working in space, SaaS means Satellite as a Service. Y- cloud in space. And you lease a an instance, and you run your workload on a satellite. In that case, you have requirements of software isolation, security, redundancy-

Reliability, quality of service and you need to map them all. And the flexibility of RISC-V means that collectively, all together, we, we can ... Maybe we will do another RVA23 specific for space or for automotive or for Edge AI

Jonathan: That,

Andrea: that- Like specific configurations- ... for the various markets.

Jonathan: That, that is actually a really interesting idea to try to tame some of that fragmentation, is to have y- a- additional specifications that say, "Okay, look-

Andrea: Yeah ...

Jonathan: to be able to be able to s- you know, for us to put our stamp of approval, RISC-V International says that this design is ready for space, you've gotta have this."

And then, the next sort of logical connection on top of that is somebody like Canonical or whoever wants to says-

... "

Jonathan: We can build a Linux image." We are going to port- we're gonna- Yes, exactly ... build an image for that. And so here is the- Yes ... Ubuntu space edition with the stamp- Exactly

of approval on it. Yeah that's that's a fascinating idea. I look forward to that happening. Y-

Andrea: The if I use I very much like the term by ETH in Zurich, the academia. And Professor Luca Benini. He gave an a very fascinating keynote at the last RISC-V Summit just a couple of weeks ago.

His theme is focusing on domain-specific accelerators, DSA. I like the term domain-specific accelerators, and it means that they are building extensions or accelerators for specific workloads in specific domains. So in that case, i- it's not unness- unnecessary fragmentation.

In that case, it is a real innovation. When you want to run standard operating system for a standard application in standard market, then you need the profile specifications like RVA23, and even more, we recently ratified the server platform. So going beyond. If I look at the hierarchy, you have the base ISA, you have all the extensions that are modular.

Then you combine an, a subset of the extensions for an application processor profile like RVA23, or we're working on an RVM profile for microcontrollers. And then the next step in the hierarchy, which is a requirement from our members, for example, in the data center space our members realize that there are so many peripherals that are close to the CPU core.

Timer, IOMMU the message system interrupts for the PCIe bus, all these core peripherals close to the core They need not be different. They shall be controlled, configured, accessed the same way. Then you can compete on the implementation, of course.

Best performance better power management, et cetera, latency.

That's the implementation side, but they all concur that they need the same specifications, not only for the ISA, but also for these core, core close peripherals. And so the server platform that we recently announced is based on RVA23- ... which means mandating support for hypervisor vectors and a few other critical extensions.

And then the server platform adds specifications for ACPI tables, specifications for these peripherals that are non-differentiating, and then specifies the standard boot architecture for RISC-V. And all this leads to the data center distributions to run seamlessly on, on the RISC-V server platform chips.

Y-

Jonathan: you knew exactly where I was gonna go next. I was gonna ask about how you boot. I have... So I love embedded devices. I've got, probably 25 Raspberry Pis around the house, and I'm a sucker for buying new things. It's oh, it's an, it's a RISC-V board that you can run something on.

Oh, sure, I'd love to having a RISC-V board I could run Linux on. Or, it's a, it's an Arm board that you can run Linux on. Oh, sure, that's different. I don't have one of those yet. And- ... the amount of time that I have spent fighting with trying to get those to boot, and going in and fiddling with the Linux kernel and, the the binary tables and all of that to try to get all the hardware to come up is just...

And so when Arm had their system ServerReady, they called it first, and then SystemReady, and I think they used UEFI in that, Yes ... and things started to just work. It's oh, that... It's so nice. And, Yes ... so I was gonna ask, like on, on these s- server RISC-V boards, what does that look like? How do we just get something to boot without having to have a device specific image to flash on there?

Andrea: Yes. That is exactly going back to a- adopting industry standards And at the same time, industry standards adding support for RISC-V. So the server platform specifies exactly the standard boot requirement architecture and boot requirement specifications. And it's, it leverages UEFI ACPI for servers.

And this was possible because the latest ACPI specifications added support, official support for RISC-V ACPI tables. So y- you see it's coming from both ways meeting each other.

Jonathan: Yeah, absolutely. I- is there some cross-pollination with the things that Arm is doing? I guess I should ask this first do you guys consider Arm to be one of your big competitors?

It seems like that might be the case, but maybe not.

Andrea: We are friendly to everyone. I think the market is growing so fast that there's room for everyone. And we are friendly and respectful to everyone as much as to all the regulations from every geography worldwide. I think that a healthy competition is is a great asset for everyone for the industry.

Jonathan: A- and then is there with things like the, a- again, I mentioned Arm's ServerReady, and it sounds similar to the RISC-V project. Has there been some cross-pollination there? Have some of those additions to ACPI been helpful to, to, to both of those pro- projects?

Andrea: I think we are all adopting the same industry standards coming from the UEFI Forum.

So again- ... it's a great value of the open standards, 'cause you can you can download and study the ACPI specifications, the UEFI specifications and adopt them. And of course, those specifications, they receive feedback from all the implementations. So they receive also feedback from all the ISAs.

So there's cross-pollination between the industry standards. Absolutely, yes. Yeah.

Jonathan: One, one thing that I've seen that I find real fascinating is the ability of the RISC-V, the core ISA, to scale both up and down. And so we have essentially microcontrollers that are RISC-V all the way up to, now with, specifically with RV823, you've got eight core chips that are r- eight RISC-V cores in there, and you could legitimately run it as your primary computer.

It might not be the most fun experience yet, but you could do it. It- Oh, it's coming ... it's, yeah. Yeah. And we're rapidly approaching that as a, a more reasonable thing to do. What's the secret sauce? What have you seen with the ability of RISC-V to scale up and down like that?

How is that possible?

Andrea: Because it's a single ISA and it's modular. If you, if we go back to the example of automotive. You have an ECU the elec- electric control unit. That must be a very tiny microcontroller, real-time, low power. Then you have the zonal controller where you may need some AI capabilities.

And you have the central compute. You have AI extensions. You have GPUs. You have NPUs. So- Outside RISC-V, you have many different ISAs. You have a different 32-bit RISC ISA for the CPU, and a different 64-bit ISA for the central compute. And a different ISA maybe based on RISC-V for the GPU or the NPU.

So you have many different ISAs RISC-V is a single one. The same single ISA, the same single instruction set can be used across all. You can configure RISC-V to be a 32-bit microcontroller for the ECU in a car- ... and focus on the real time extensions. It's the same ISA that you can configure to be 64 bit, but it's still the same ISA, the same instruction.

It doesn't change- ... for the zonal controller, and you can add vector extensions, and in the future, matrix extensions to have AI inference inside the zonal controller pre- preprocessing data coming from the sensors. And the same ISA without change can be used in the central compute. Then you would add extensions like hypervisor support.

So the same ISA, the same programming model, the same tooling can... The same expertise can be used across all.

Jonathan: Yeah. That's... it's super cool to see. And so you see as a result of that, RISC-V pop up in maybe some unexpected places. I'm pretty sure Intel runs r- a little tiny RISC-V core as their a- as their sort of s- root of trust in most Intel processors.

And I think I've read about hard drives that have RISC-V process. It's, we- we're part of Hackaday now, and so I remember there was a there was a particularly interesting story where someone says, "I installed Linux on my hard drive." He's no. I don't mean I wrote Linux to the hard drive.

I meant, I hacked into it and I'm now running Linux on the RISC-V processor in my hard drive." Oh.

Andrea: I love this. Thank you for sharing it.

Jonathan: I'll see if I can dig that link up for you-

Andrea: Yeah. Yes, please ... '

Jonathan: cause that one was particularly fun.

Andrea: Yes, please. But- Yeah, RISC-V is popping up everywhere.

As you say, it started in the deeply embedded microcontrollers from Western Digital from the early 2015 when the RISC-V Foundation was re- i- initially created. And Nvidia was also one of the first to adopt RISC-V in those years. And Nvidia has been shipping RISC-V in every single GPU between 10 and 40 RISC-V cores in a single GPU.

In 2024 Nvidia were our guest speakers at the RISC-V Summit, and they publicly explained, and that's a very interesting keynote. They explained how they use RISC-V in many different ways inside a GPU for many different functions, and you can find that on YouTube, or we can provide the link later for- for your for your guest. And they evaluated that just in 2024, Nvidia shipped more than one billion RISC-V cores in the GPUs. Qualcomm in 2022 estimated that they had shipped about 600 million cores in wearables, and just a few weeks ago they updated the they've estimate to two billion cores in wearables.

Infineon one year ago announced that their entire automotive microcontroller roadmap is based on RISC-V. Meta is using RISC-V in their Meta training and inference accelerator, the MTIA chip. Google is using RISC-V in the Coral NPU, which was also released as an open source project- ... last year.

And then you have AI accelerators with hundreds of cores by Tenstorrent, Inspire Semi. You have the latest NPU by MIPS, all using RISC-V. And then we have the application processors coming this year

Jonathan: There are d- do you think we've passed the point to where there are more RISC-V cores than there are people?

This is my metric for when talking to a project that is really popular, and so I asked this, I asked Daniel Stenberg this, the guy behind Curl. I'm like, "Are there more Curl installs than there are people?" He's "Oh, definitely."

Andrea: The SHD Group estimates that RISC-V will pass the 35 billion SOCs in 2031.

And every SOC can have more, multiple RISC-V cores, multiple. Just as I said, the Nvidia GPU has between 10 and 40. So I think that we by large, we passed the number of humans on Earth already.

Jonathan: That's, that is so wild to me. And of course with the with the AI boom and just the way all of that is growing I don't think any of this is slowing down.

I think we're just continuing to accelerate. And you have you have serious contenders talking about, putting cores up in satellites and doing data centers up above us, and- Yes ... it's just it is incredible to watch. It, we are in a very interesting transformational moment in in human history right now.

Andrea: Yeah. And you were also hinting at using it as a main computer-

...

Andrea: Right? And yeah I'm happy to touch on that as well. Thanks to Deep Computing we have had RISC-V based laptops for the last few years. With the DC Roma laptop, the first generation, the second generation, and then Yuning from Deep Computing partnered with Framework the modular laptop company.

Yes. The latest RISC-V based Framework m- motherboard, based on the SpaceMID K3- ... you sh- you should try it. Believe me, you should try it. You will get 4K YouTube video playback, very fast browsing office applications. So it's still a machine targeting developers in terms of price tag. It's m- but you should try it.

We were really planning to purchase as soon as it's available in quantity, purchase a few for the RISC-V staff, and use it- ... at events, and eating our own dog food.

Jonathan: Absolutely. I remember I reviewed, this has been a couple of years ago now, it was, Vision Five, I think Yes.

I r- I reviewed that, and I set it up with a monitor and I s- I tried to use it as a desktop for just a little while, and that was not a great experience as a desktop user. But in my review, I made the statement that it's just good enough for developers to start actually doing development- and compiling their stuff on it. And so it's not gonna be great for running as your desktop, but it is gonna be transformational for the RISC-V ecosystem as a whole. And I think we're now seeing some of the results- Yes ... of that kind of work with, you know-

Andrea: Yes ...

Jonathan: players

Andrea: Ubentu- We don't- ... and,

Jonathan: and all

Andrea: of that.

Yes. And the latest RVA23 chips are bringing that level of performance. The SpaceMeet K3 is just the first one that has very good performance. It also running local LLM models. But there are so many other RVA23 silicon that, that are becoming available. This is the year of the RISC-V application processor, really.

Jonathan: Maybe not the year of RISC-V desktops and laptops for everyone quite yet, but it ... do you ... W- when you allow yourself to dream, do you think about that one of these days Intel and AMD is gonna have to compete with RISC-V? Is that a future that you see?

Andrea: Our goal is to ensure that RISC-V is the first or default choice for new designs

Jonathan: That's fair

Andrea: the default ISA for new designs.

Jonathan: And that, that encompasses a lot. That is actually quite the quite the aspiration.

Andrea: Yes.

Jonathan: But on the other hand, so many of these devices have a RISC-V core in there. I suppose one might say that you're pretty close to that.

Andrea: Thank you.

Jonathan: That's fun.

So what about ... And I touched on this briefly, the idea of developers getting ahold of RISC-V.

Andrea: Yes.

Jonathan: What does the sort of the ecosystem look like for the tool chain, the compiler, the developers, and I'm sure this is something that you guys have worked on quite a bit, is to- Yes

to grow this ecosystem in the community. What does that look like?

Andrea: Yes. We are focusing on the developers from multiple angles. On one side, we have been purchasing and shipping the latest development boards over the last few years. In 2024, we shipped more than 200 boards to key developers, including tool chain operating systems.

In 2026 in collaboration with RISE, the RISC-V Software Ecosystem Project, we are setting up a build farm, a RISC-V based build farm with native GitHub runners in collaboration with the open source lab at the Oregon State University. We also have the first RISC-V based commercial cloud service provided by Scaleway in Europe so that's one, one axe is, one axis is hardware availability.

The second one, as you mentioned, is the tool chain work. So we we are in close collaboration with the tool chain projects not only GCC and LLVM but of course, we also have many members who provide their own tool chains like Green Hills, IAR, TASKING, embikasm, they're all working on tool chains.

So the point is that, for example, when we release the RVA... We ratified the RVA23 profile specification. Patches to add support for RVA23 in GCC and LLVM were already being reviewed by the maintainers. And then Rise is collecting funds to direct them to optimization work. So Rise has been funding work to optimize support for Python, LLVM, Go, and also projects like PyTorch and Iri or Llama CPP.

We have been investing together with Rise to add RISC-V as an official ISA in the Yocto Project. In just f- we, we upgraded our membership to the top tier the platinum level in May 2025, and just five months later, RISC-V was the the third officially supported ISA. Today, Yocto supports x86 ARM, and RISC-V- as the three official architectures. So it means that for the developers, Yocto is not only an embedded Linux and a set of tools to optimize and build your embedded Linux distribution, but it also means that you have an LTS support for the file system that is using the kernel LTS, and most importantly, it's all using upstream Linux support.

And this was possible thanks to the collaboration RISC-V International and Rise together.

And it's a major achievement for us. And the third axe, so I mentioned hardware availability, the operating system, and tool chains, and the third one is the trainings and the developer experience. So continuously adding new training courses to our free catalog on our website.

I mentioned the designer RISC-V CPU core, my favorite one, but we continuously add new trainings for real-time operating systems, for porting software from other ISA to RISC-V, or optimizing software for the RISC-V vector extensions

Jonathan: Yeah, interesting. The the training that you guys provide, is that freely accessible?

Can someone just-

Andrea: Yes ...

Jonathan: jump on the-

Andrea: Just go on the riscv.org or RISC-V.org as you would spell it or type it. And then you have the community, and you have the resources and the full catalog over free online trainings.

Jonathan: Wow. It sounds like that would actually be a, if someone was, say, in high school or starting college and really wants to break into the sort of MCU embedded environment- Yes

that would be a really good place to get started. Yes. Put that on your resume that you've worked with RISC-V.

Andrea: And we... we also have the mentorship program every year where we select multiple students and mentor them on… And they deliver real results. They do real work.

Jonathan: Yeah, absolutely.

What sorts of what sorts of work, what, where do they get em- embedded at when, in that internship program? What kind of work can someone expect to do?

Andrea: It varies a lot. Some worked on enabling kernel CI on RISC-V and kernel testing. Others are working on tools that automate documentation and consolidate the, or get better organize the documentation for the various extensions, and generate programmers reference manual and so on. So it varies a lot.

Jonathan: Yeah. Interesting. What what are some weird places or weird things that people have done with RISC-V that, that you're aware of? I feel like everyone that's in the tech industry has a story of some sort.

I built this tool and someone used it for something completely different than what I intended it for. There, there's gotta be some oddball RISC-V use cases out there.

Andrea: Oh, we in one of the last summits, we were offered one of those interactive teddy bears. That runs on RISC-V.

That's pretty good. Yeah. That's pretty good. And more is the professional one is the humanoid that ran the marathon in China- Okay ... a couple of months ago. That was running on the Space Mid K3 chip. Oh, that's cool. RISC-V in space. RISC-V was on one of the last moon lunar lunar landers.

Okay. And then today I was reading somebody designed a GPU using 8,000 RISC-V microcontrollers interconnected.

Jonathan: Really?

Andrea: Yes.

Jonathan: That's impressive. Massively parallel indeed.

Andrea: Oh, yes.

Jonathan: A- and so l- what what do you see as you rub your crystal ball and think about what comes next for for RISC-V?

What are some things that you're excited about for the future? What do you see coming down the pike?

Andrea: In short term, all the RBA 23 application processors. SiFive, Andes, Tenstorrent, Akeana, Alibaba BOSC, Nuclei, Spacemi. There are so many that are coming up. At NextSilicon EPiC SEMI.

I think at the last RISC-V Summit a few weeks ago, we announced more than 10 RISC-V application processors. Many of them have server-grade performance.

So in short term, this is super exciting. Then ratification of the matrix extensions is something that is very important. The completing the work with ISO IEC I really want to get through and make sure that RISC-V, the RISC-V ISO manuals can be properly evaluated as a possible ISO standard.

And the other thing I really want to continue investing in the idea of the developer workshops. W- this is something we started at the last RISC-V Summit North America in October twen- October last year, and then Summit Europe a few weeks ago. So at every RISC-V Summit, we're now dedicating one full day to hands-on labs.

And just a couple of weeks ago the fee for this lab, the cost was, the price was 30 euro. So it's really just to ensure no-show, that's all.

And we had a hardware track, a software track. We had labs running an open source RISC-V design where the authors broke the system very long.

So while running some assembly test, suddenly you got an exception. And the developers had to find where in the system very long it was broken. That's alwa- Can you imagine that? That's always fun, to break your tooling. Can you imagine that? Yes. Lauterbach had something similar. They enabled 24 debug sessions, debug tools in parallel, independent.

So we had multiple developers on each station, so 100 people. And Lauterbach demonstrated how you can do advanced trace and debugging on RISC-V. And then they ran a challenge. There was a software running with some memory leakage or some bug in it. And these 24 teams had to find it and fix it as quickly as possible.

We had workshops on running ExecuTorch or Edge Impulse AI inference on RISC-V or running trusted execu- execution environments and mitigating risks from the threat models. So all these were hands-on labs. And this is something that we will continue investing, and just sharing ideas to organize the next workshop is super exciting.

It's so much fun. So much fun when you see what can be done.

Jonathan: Yeah. Have ... Some of my listeners hate it when I ask about this, but it is the world we live in. Ha- have the flavor and the way those workshops work, has that changed radically because of LLMs and AI in the last, say, six months to a year?

Andrea: No. No, not yet. Oh. Not yet.

Jonathan: Interesting.

Andrea: Maybe in the future. Not yet.

Jonathan: Oh.

Andrea: Oh, one thing, yes. Do you- I think it may be used to generate more design verification tests from our members. But for these workshops we are really running them with a human brain. We want to challenge the developers.

That's why they are joining these workshops. They want to learn hands-on. They don't want to just prompt the AI to do it for them. Correct. And I think it's super exciting. At times I would like to go back being a developer and being part of these workshops.

Jonathan: Yeah. That, there, there's only so many things that we get to travel around and go to, and yeah.

It's one of the downsides of being the CEO. You don't get to, you don't get to be as hands-on with some of the things that you really enjoy. I get that. I too am CEO of a company d- a small company, but still I have to balance those things too. I'm lucky that I get to write some code still, but I see a, maybe a time coming before too much longer that'll come to an end, and-

Andrea: A- and that's why I enjoyed so much the interview process with Calista two years ago, when she interviewed me, and then the board interviewed me.

And the founders of RISC-V. 'Cause that gave me the opportunity of studying all the ISA manuals, and even I had fun in taking some code in C and write my own RISC-V assembly. And I wa- I was good at arm assembly in the past. So I took this C code, I wrote it in arm assembly, then in RISC-V assembly, and I appreciated the differences.

And then I took that course on designing a RISC-V core from the website. So both the software side of a RISC-V ISA and the hardware side, and I really enjoyed that, You- ... that interview process.

Jonathan: You really understand RISC-V well. I don't know that I've ever talked to a CEO, somebody at the head of a company, that has the technical understanding of what he's working with that you do.

That is quite impressive.

Andrea: I better understand the rest then.

Jonathan: Yeah, sometimes that is the challenge. All so I... Boy we've gone through a lot. Is there anything that we didn't cover that we should have? Is there anything that I didn't ask you about that you wanted to make sure and mention to folks?

Andrea: The developer workshops and the laptop were really the things that I thought were maybe not on, on your mind, so I mentioned them.

Jonathan: I must say, I have the I have the Deep Computing store page pulled up.

Andrea: Oh, okay.

Jonathan: I have Framework laptops. I really like the Framework laptops. And yes this particular main board looks very interesting.

Don't tell my wife, I may be about to spend more money. The really funny thing about that is that she watches the show, so she's probably out there, muttering at me. Oh, so she knows already. She already knows. She's checking

Andrea: your credit card statement now.

Jonathan: Yes, of course. Don't look too close.

So what, W- y- RISC-V is going to space. Do you foresee a big uptick there? I, so I went and looked f- for one thing. Yeah. I was interested. The the Ingenuity rover the helicopter running Linux on Mars. I, I thought "Was that RISC-V?" No, that one's running ARM. But, Yes

Maybe the next helicopter will be RISC-V, right?

Andrea: Oh, RISC-V was in the lunar lander last year And the interesting part is I attended a RISC-V in Space workshop organized by the European Space Agency and Geissler in 2025 last year. There were maybe 200 speakers in the room, 200 projects based on RISC-V.

It was unbelievable. And we had another RISC-V workshop at the last summit just a few weeks ago.

And we had representatives from the European Space Agency, from NASA, from Microchip, from Geissler E4 Computing, and they were all explaining why they need RISC-V, why they need an open standard, why Geissler moved from Spark to RISC-V now.

Why they chose Spark in the first place, and now RISC-V. It's, it is so fascinating. Yeah. So fascinating.

Jonathan: I I did have a thought earlier, and it just comes back to me. Has RISC-V had any problems with things like export controls?

Andrea: No.

Jonathan: I- is this because you're intentionally a European company, or is it because-

Andrea: No

everything is open? No.

Jonathan: Or how have you- Because we- How have you avoided that?

Andrea: Because we are extremely scrupulous and respectful of all the regulations worldwide. And because we are a standard. We are an industry standard. We do not produce any implementation, any reference implementation, any artifact that would be a technology that gets exported.

We don't do that. We just do PDF. Remember? Remember? We just do PDF, like USB.

Jonathan: I, I think this is going to be the show title, We Do PDF. We

Andrea: Do PDF. Why not? No I'm s- I'm serious. We are laughing together, but I'm serious. Doing in- international open standards means that it's a standard.

And the implementation, the technology gets developed locally where the members are. You can design a USB mouse or USB pen drive in Silicon Valley or in India or in Europe or in Brazil.

And that will be a local design. But the standard is global, and the same is true for RISC-V. Yeah. No, that certainly makes sense.

That- that's why this recognition from ISO/IEC is so important to us, that we got accepted as a PAS submitter, as a standardization body. It's very important that we are officially recognized as a standardization body.

Jonathan: Have, has there been any has there been any patent problems with RISC-V over the years?

Andrea: No, we don't do any patents.

Jonathan: But I g- I guess the way that I would imagine that working is, you get an email from, and I'm just ... I'll pick one at random. You get an email from Spark, says, "Oh your ISA violates one of our software patents."

Andrea: No.

Jonathan: Nothing like that? Oh, lucky you guys.

I think it probably helps that it's based on something that came out of academia back in the '80s. And so a lot of those things that someone would say, you could just point at and look, this guy came up with this in 1982. The patent on that's already expired." Yes. "Go away."

Andrea: Actually, we are the fifth generation of the original one-

That inspired all the other RISC-V designs.

Jonathan: Yeah. That helps. That helps a lot, being, being the original. We did it first. Oh, that's great. All right. I do have a couple of final questions that I'm required to ask everybody, and I get in trouble if I don't. I get emails if I forget these. You personally, what's your favorite text editor and scripting language?

Andrea: My favorite text editor was Zap

Jonathan: Okay

Andrea: That was a text editor that was, I was using when I was programming on an Acorn Archimedes. That was one of the first machines based on the ARM3 processor- ... and the RISC OS operating system. And at that time, I used the Zap editor. I loved it. I loved it.

Jonathan: That's a throwback.

Andrea: Yes. What do

Jonathan: you use these days? Surely you don't run Zap in an emulator.

Andrea: No. No, these days I just use a simple text editor available on on my laptop.

Jonathan: Wh- which one, though? Do you go for VI or Nano or ...

Andrea: ... w- Ah, let me check. No, the name is just Text Editor. Yes, Text Editor.

Jonathan: Okay.

Andrea: As simple as it is.

Jonathan: As simple as it gets. Yes. A- and scripting language, if you have to, if you have to write some script code?

Andrea: I was using the ... The one I used the most in the early days was the the MS-DOS Batch

Jonathan: Yep, yep. I've have some experience with that from a long time ago.

Andrea: I'm sorry i- I have some gray hair.

Jonathan: Oh, don't look too close at me. I, I've- I- ... I am gaining some as well.

I- It

Andrea: may not... it may not sound that fascinating, Zap or Batch.

Jonathan: I got my start programming with Microsoft QBasic. I'm old enough to say that. But I've have not done anything with the Acorn, with the Archimedes and or any of that, so I fit somewhere in there.

Okay.

All right. Andrea, it has been a blast to get to talk to you. Thank you so much for coming, and, Oh, my pleasure ... I'm glad we got to- Thank you so much

Andrea: for inviting me. Thank

Jonathan: you so much. Yeah, glad we got to talk about it. Really enjoyed it. Yeah, I did as well. Thank you so much, sir.

Andrea: Thank you.

Jonathan: All right.

That was Andrea Gallo talking about RISC-V and RISC-V International, and boy, had a great conversation there. We've got some fun shows coming up. Next week we're talking with Neriman Jelva about Pewter. That is the desktop operating system that runs in your browser. I have questions about that. And then the week after that we're talking again with Michael Meeks of Collabora.

And then the week after that we have a returning guest, Francois Proulx, about Smoked Meat, and that's all about security in your CI, like in places like GitHub. Very important. We do have some openings after that, so if you or your project you think should be on the show, you should let us know. Drop me an email.

It's floss@hackaday.com, and we'll get you scheduled up. Other than that, just wanna say thank you to everybody that's here, whether you watch or listen live or on the download, and we'll be back next week on Floss Weekly.