The Bottleneck Isn’t the Chip with Bubble boi | EP 166

Mr. Bubble is world class at explaining very technical concepts in layman terms. In this episode I wanted to chat through the 0 to 1 of the chips, racks, packaging, the memory hierarchy, scaling up and scaling out.

We spend a lot of time mapping computer-architecture primitives directly onto the AI factory and examining where value is actually going to accrue as packaging, HBM, and the next memory tier mature.

At the center of the conversation is the belief that the bottleneck is no longer designing a faster chip, it is the physical stack from silicon to rack. While the frontier labs settle into a more mature “closed demand” phase focused on their own silicon, their own scale-up domains, and capturing the value themselves.

We also get into his view on AI alignment and the future of Labs.

We discuss:

• The 0 to 1 of chips: what actually has to be true before a die is useful
• Why packaging is the new Moore’s law
• Racks as the real unit of compute
• The memory hierarchy after HBM
• Scaling up vs scaling out, and why they get confused
• What the labs actually want from the supply chain
• AI alignment, and whether the labs are aligning the world or just themselves
• The future of Labs: closed frontier, custom silicon, and who gets the model

Timestamps:

0:00 – Introduction & Why Hardware Is the Real AI Conversation
8:00 – 0 to 1 of the Chip
18:00 – Packaging as the New Moore’s Law
28:00 – Racks, Trays, and the Unit of Compute
38:00 – Memory Hierarchy: HBM, DRAM, and the Next Tier
50:00 – Scaling Up vs Scaling Out
1:02:00 – AI Alignment
1:10:00 – The Future of Labs
1:17:00 – Closing Thoughts and Where Value Accrues Next